1. Field of the Invention
The present invention relates to a D/A converting device with an offset compensation function and an offset compensation method of the D/A converting device. More particularly, the present invention relates to a device and a method of compensating DC offset of a D/A converter built in a digital radio communication device.
2. Description of the Related Art
In the digital radio communication equipment, respective I(In-phase), Q(Quadrature) signals, which are subjected to the digital modulation, are D/A-converted, then coupled in the radio frequency portion of the radiotelephony, and then sent out from the antenna as the radio signal. Ideally, analog output voltage of the D/A converter should coincide with ideal analog output voltage (analog output voltage without DC offset) that corresponds to digital input value. Actually, the DC offset is generated between the actual analog output voltage and the ideal analog output voltage because of various factors.
In the case of the differential output type D/A converter, if the DC offset is generated between differential outputs (I+ and I−, or Q+ and Q−) of the D/A converter, which correspond to the I signal and the Q signal respectively, (i.e., input/output characteristics of differential outputs of the D/A converter is different), a phase between respective I, Q signals is shifted to generate a transmission error. Therefore, the characteristics of the D/A converters must be made uniform by canceling the DC offset between the differential outputs of the D/A converter.
In order to cancel the DC offset between the differential outputs of the D/A converter, the DC offset between the differential outputs of the D/A converter in response to test data must be measured in a test mode where no input signal is present. For this purpose, a comparator (a voltage comparator) is employed.
In the prior art, the next digital input of the next D/A converter is derived by adding +1 (high level) or −1 (low level), which is obtained on the basis of the result of the voltage comparison executed by the comparator, to the current compensation value (its initial value is 0), and then subtracting the new compensation value from test data. Then, the above procedures are repeated until the polarity of the comparator is inverted. The compensation value obtained when the polarity is inverted gives the compensation value (control data) to compensate the DC offset between the differential outputs of the D/A converter. There is the technology to cancel the DC offset between the differential outputs of the D/A converter by correcting the input data based on this compensation value (see JP-A-7-202693, for example).
JP-A-7-202693 (FIG. 1, FIG. 2, etc.) is known as a related art.
However, the DC offset actually exists in a comparator that detects the DC offset in the D/A converter in a single output type D/A converting device and in a comparator that detects the DC offset between the differential outputs of the D/A converter in a differential output type D/A converting device. Normally, the DC offset of the comparator is designed to be suppressed within several mV.
However, according to the study of the inventor of the present invention, it was confirmed that in some cases the DC offset of the comparator itself is in excess of 20 mV due to variation in transistor size, LSI production process conditions, etc. In particular, the DC offset of the comparator tends to increase as the transistor size is miniaturized.
The DC offset contained in the comparator causes an error in measuring the DC offset (containing the DC offset between the differential outputs) of the D/A converter. As a result, the precise measurement cannot be carried out if the DC offset of the comparator itself is large, and thus the DC offset of the D/A converter cannot be perfectly removed.